ZX-Badaloc     Reloaded

Full Project History


FPGA V1.06: Added AY-3-8912 sound chip emulation support (using the YM2149 core by MikeJ of www.fpgaarcade.com). A sigma-delta DAC converts the 8-bit output into a single digital signal. A simple external RC integrator is then used to drive the speaker amplifier. Audio output is demonstrated in the Pac-Man emulator video.

ZX-Com V5.4: Capability to import/export raw binary data from an sd-card snapshot made easier. This allows creating a ram-backup snapshot using a ResiDos 'nvram backup file' (residos.nvr) so it can be restored by bootrom firmware.

FPGA V1.05: The 'Rom Services' address trap ($25) is now disabled by default. This improves compatibility and solves an issue with the pac-man emulator written by Simon Owen.

FPGA V1.04: Bugfix: Ram Bank 0 is now (properly) writable when mapped on 0-$3FFF space using the special memory addressing mode of +2A/+3 models (register $1FFD). This bug prevented a PAC-MAN ZX-Spectrum emulator from running. Thanks to Simon Owen (author of the emulator) for the support in tracking down the problem.

BootRom V1.01 and ZX-Com V5.3: Support for ULA+. Color palette is now detected and saved / restored in both sd-card and rs-232 snapshots.

FPGA V1.03: The ULA+ color register is now RD/WR. This will be useful in order to backup a color palette into snapshots and detecting if a game is using ULA+ features. See the I/O register's page for details.

FPGA V1.02b: Added an OSD function that replaces the external LCD display for breakpoints, system monitoring, etc.

FPGA V1.02: Added ULA+ support. Thanks to Alessandro Dorigatti (who did it first) for the support and source code.

FPGA V1.01: All changes up to latest Xilinx's board VHDL (1.32b) merged to the project: Picoblaze processor, encoder/switches/lcd display are now working as on the other board.

First version for Nexys2 board. The starting VHDL source 1.00 is a reduced version written for a Spartan 3A (Avnet) board, in turn coming from V1.11  29/11/2008 of the Xilinx 3E version. This made things easier because there is no DDR controller nor Picoblaze processor. The Z80 bootrom comes from latest (V0.99b) version for the Xilinx board: only the name string printed on screen has been modified. The version number is now 1.00. The VHDL rom which boots the system is the same written for the Xilinx board with no modifications.

FPGA V1.32b: The prescaler's slowdown takes now (properly) place from the very first step of the encoder setting.
ZX-Com V5.2b: RS-232 buffers enlarged so that a full 64K (65536 bytes) block can be transferred in one shot. The Flash --> Get Rom Bank command works now on badaloc_nano too.

Corrected a mistake in the 'quickstart' page about the RS-232 cable

Bootrom Firmware V0.99b: ResiDOS 2.08 signature correctly located in ddr memory so that the [R] ResiDOS option is displayed on main menu'
PicoBlaze Firmware V1.13: FPGA Breakpoint registers are now continuously updated, in case of FPGA reset (picoblaze is insensitive to reset)

ZX-Com V5.2: Bugfix: the fastpage bank is now properly initialized with real hardware value when the program connects to the clone.
$54DF, $64DF and zx-mmc+ $7F registers can now be manually edited in the Snapshot Editor.

FPGA V1.32: The breakpoint logic reacts to any memory access and not only on opcode fetch (as before). For example, this allow triggering on screen writes.
FPGA V1.31: Added an internal reset generator based on a counter, to overcome the lack of a true external reset signal. The counter is restarted by the button that was previously the reset signal itself (BTN_NORTH). The reset is also held active until the main PLL is stable (locked).
The NMI button (BTN_SOUTH) is no longer hard-wired to T80 NMI_n pin. PicoBlaze reads the button and handles T80 NMI signal through an I/O port. This allows a good button debounce and let the picoblaze issue an NMI for other reason (none by now).
PicoBlaze Firmware V1.12: T80 NMI handler added on BTN_SOUTH.
Bootrom Firmware V0.99: If an NMI is received while already servicing an NMI, then a warm_restart is performed. The bootrom firmware main menu is entered without reloading the DDR bank from SPI flash rom, saving time. This function required a good NMI button debounce (handled by picoblaze).

PicoBlaze Firmware V1.11: BreakPoint Address editor on SW1. Rotate the encoder to edit current nibble, then press to select next nibble.
Bootrom Firmware V0.98e: Bugfix: The sd-card snapshot used to save DDR_MSB register at offset +60 in the data record of the snapshot, which has already been used by ZXMMC+ to store it's FastPage register. Now +61 byte is used, and '00' is loaded on +60 (which is an acceptable default for zxmmc+ to load it).
If SW2 is on, 1 second delay is added after any sd-card snapshot restore, allowing the screen to be visible for a moment
ZX-Com V5.1b: BugFix: ZX-Badaloc / ZXmmc+ FastPage registers and DDR_MSB registers are now correctly displayed in the properties of sd-card snapshot in the 'Edit Fat' of the sd-card menu

FPGA V1.30: New BreakPoint logic added.
PicoBlaze Firmware 1.10: BreakPoint management: NMI and Single-Step. The first mode issues a NMI on address match; the second will enter Single-Step mode. While the purpose of the second mode is quite obvious, the NMI is very useful when saving snapshots. If the breakpoint address matches the end of Tape loading routine, then a perfect snapshot can be saved just at the end of loading from tape (the normal response to NMI is the activation of bootrom firmware, with snapshot management). Note that in current version the address is fixed to the tape loading routine ($05E2). An address editor will be added soon to the PicoBlaze firmware.

FPGA V1.20: New registers added for PicoBlaze support: a Z80 clock prescaler that can slow down execution to one Mem - I/O cycle every 2 seconds and single-step capability; ability to change the Z80 clock speed; switches/buttons/encoder/leds/lcd are accessible.
PicoBlaze Firmware 1.00: the Z80 clock speed can be adjusted on the fly by rotating the encoder knob. When lowest possible frequency is reached (3.5MHz) then a 'prescaler mode' is entered. In this mode, there are 24 steps for slowing down the system: slow enough to be able to read instructions execution on the LCD display. A single-step mode is also provided. The 7 previously-free leds will now display a moving pixel which runs accordingly to the Z80 speed. A complete cycle means 500.000 opcode fetch executed. See details in the controls page.

FPGA V1.13: New PicoBlaze processor added to the project. It displays several information on the onboard LCD:
First row = registers content: $7FFD, $1FFD, $24DF, $34DF, $54DF, ddr_msb;
Second row: Z80 Address / Data bus, operation performed (MemRd/MemWr/IORd/IOWr) slowed down to a rate of approx 2 updates per second, and finally the Z80 current clock speed.
Some snapshots and sd-card backups provided in the zx-com package (see the 'quickstart' page)

FPGA V1.12: Small changes for joystick programming control, which no longer uses the previous 'flashrom_write_enable' control bit. This allows the parallel flash to be write protected the same way it was on the original cpld-based clone. Other smaller optimizations. Should be used with bootrom V0.98d.
Bootrom Firmware V0.98d: the joystick programming routine has been updated to match the new fpga logic.

Badaloc Nano for Avnet 3A evaluation kit now available
ZX-Com 5.1 with hardware definition for Badaloc Nano

FPGA 1.11: T80 patch by Mike J with correct I/O timings
Bootrom Firmware 0.98c: INI unrolling is now used, thanks to T80 patch and improved SPI clock speed.

FPGA 1.10: Improved SPI interface clock speed: 28MHz instead of 21 of the CPLD-based original clone. This is useful due to the fact that the processor can be ran at higher speeds here (28 and 42MHz were not available on the original clone). It is now possible to access the sd-card with INI/OUTI at full speed with T80 running up to 28MHz, provided that they take 16T on the processor. DDR is still at 85MHz as in the 1.09b version.

Unofficial T80 patch by Mike J: IN and OUT instructions are now (properly) executed in 4Tstates instead of 3.

Unofficial ResiDOS 2.08 Version for zx-badaloc available from Garry Lancaster: the %SPEED command now supports 28 and 42MHz (parameter 6 and 7 respectively).

FPGA 1.09b: More accurate DCM and clock buffers placement allows running the DDR at 85MHz (under testing). This reduces the T80 wait states needed for memory access when the processor runs at higher speeds.

Bootrom Firmware 0.98b: Minor changes in the joystick, flashrom and 512K ram backup menus.

Bootrom Firmware 0.98: Fixed a bug in the rs-232 snapshot upload, thanks to Victor Trucco.
Added support to programmable joystick (beta). It is now possible to map any of the first 10 joystick inputs to any of the zx-spectrum 40 keys, giving absolute joystick compatibility with every program and game ever written. Requires fpga 1.08 or higher. Joystick data shift reverted, so the lower side of the 16 bit in the fpga will contain data from the first 74HC166 chip. In this way it is possible to build a joystick interface with just a single IC and 8 inputs, readable on first 8 bits by default on kempston port. Joystick schematic updated.

FPGA 1.08: The 16 joystick inputs can be mapped to any of the 40 zx-spectrum keys. A single input can "press" more than one key simultaneously. The bootrom firmware 0.98 is able to program sd-card saved joystick layout into the new fpga logic, but due to sd-card snapshot layout, only the first 10 inputs are used.

ZX-Com 5.0b: Small fix for older .snap files (rs-232 saved snapshots): newly used bytes are now properly set to zero if not present in the release used to take the snapshot.

Bootrom Firmware 0.97: Added BBC Basic menu, ResiDOS detection (in ram), 512K Ram backup on sd-card (this can be used to save ResiDOS installation), support for zx-com V5.00 with

ZX-Com 5.0: Overall cleanup, support to new fpga version registers

FPGA programming file V1.07: the ZX-Spectrum brightness attribute is now provided on three I/O pins. Wiring these pins to the VGA connector (through proper resistors) will bring the full color capability of the original machine. See the download page for instructions and pictures.
New bootrom Firmware V0.96: it is now possible to select 28 and 42MHz Z80 clock for any sd-card based snapshot.

FPGA programming file V1.06: the DDR_MSB register (higher 6 DDR address lines, selecting one MB out of 64 megabytes) is now only effective for 'fastpaging' memory accesses. This means that in normal operation (48/128/+2A/+3 Spectrum) the first MB of DDR will be accessed, regardless of DDR_MSB register's content. This allows even a BASIC program to run within 32K of 'steady' memory, while accessing up to 64MB banked in the upper 16K ($C000 - $FFFF) by 'fastpage' mode (see registers documentation).

16 inputs Joystick interface added. Due to lack of available I/O on easily reachable connectors on the xilinx board, two 74HC166 are used to serialize 16 inputs and send them to the FPGA with just two wires. Reading $1F (Kempston) port will return data from first 8 inputs by default. Writing a '1' on D7 of same port will select upper 8 input lines. The original zx-badaloc has 10 programmable inputs, while current FPGA implementation still misses the programmability (input / keyboard association). Schematic is available.

Bootrom Firmware V0.95: minor updates to bootrom and zx-com: Flash -> Get ROM Bank is now (properly) redirected to the SPI Chip.

New Bootrom Firmware V0.94 and ZX-Com V4.6d: restored the 'FastPage dump of entire RAM chip' command. Added the 'FastPage dump of entire ROM chip'. These commands allow dumping 512K of data (from "RAM" or "ROM" area of the active DDR megabyte, lower or upper half respectively).

New Bootrom Firmware V0.93 and ZX-Com V4.6c: restored the 'ROM Send' commands from zx-com. It is possible to send a 16/32 (and now 64) K rom for evaluation purposes. The rom will be executed in a separate DDR area, normally at +1MB offset.

A small read cache (4 bytes) avoids DDR activation (which may lead to Z80 wait states) when the CPU reads a byte inside the last accessed doubleword (the DDR controller is 32 bit wide). This increased average performance.

The DDR controller allows now byte wide write operation, allowing the access to the entire 64MB space, thanks again to
Klaus Rindtorff.
ZX-Spectrum 128K, +2A / +3 special memory mapping has been implemented. The clone can now run as one of these machines and is compatible with ResiDOS and +3E ROMs by Garry Lancaster, as the original clone did.

A DDR controller has been embedded in the project thanks to
Klaus Rindtorff, who provided a modified version of the Plasma CPU ddr controller by Steve Rhoads.
Many firmware features have been ported from the original ZX-Badaloc version, so that the current FPGA implementation works as a fully functional 48K ZX-Spectrum and is capable of taking/restoring snapshots to SD-CARD or RS-232 using the ZX-Com Win32 program. Sinclair roms and the bootrom firmware can be flashed on the onboard SPI FLASH chip using zx-com and a rs-232 port. Even the xilinx .bit configuration file can be programmed in the spi flash this way.

The 'context switch', a zx-badaloc feature which activates an alternate rom when a NMI is detected is now fully working, thanks to the additional memory now available. This alternate rom is the BootRom firmware, running in 16K blockram in the fpga (while all other roms are now copied into DDR banks at power-on from the SPI Flash chip). The context switch allows transparent interruption of any activity and handles rs-232 communication with zx-com (any memory area can be inspected) so that snapshots can be saved and restored through both rs-232 or sd-card.

NMI is generated when a character is received from rs-232 port or when the SOUTH button is pressed on the board, and is handled by the bootrom firmware.

Further porting of the ZX-Badaloc original Bootrom, now programmed in the SPI Flash as default power-on ROM (at address $10 00 00 of the M25P16 chip, which is loaded by the tiny bootloader). The system now displays the standard ZX-Badaloc main menu with sd-card content (snapshots saved on card by ZX-Badaloc or ZXmmc+). It is also capable of loading 16K snapshots from both sd-card and RS-232 (ZX-Com), thanks to a temporary routine which reads a 48K sinclair ROM from SPI Flash address $11 00 00 into the 16K blockram mapped at $0-3FFF just after sd-card snapshot restore. This overcomes the lack of real ROM space (until the DDR controller will be hopefully added to the project).

First SD-CARD slot soldered on the prototype adapter on which the Tape Interface was built. Successful communication with a 1GB card.

Tiny Bootloader totally rewritten with additional SPI read/program/verify capabilities. It is now possible to program and compare a Xilinx's .bit file into the onboard SPI Flash without a jtag cable, just through the serial link and ZX-Com.

SPI programming routine for the onboard M25P16 flash chip successfully tested. New option in ZX-Com program which adds the capability to store the transmitted rom at a fixed flash offset. This rom image, when found at power-on, is then used to start the ZX-Spectrum after a few border color cycles. A Sinclair basic SPI flash programming example is available and will be online soon.

Minor bugfix in Spectrum screen logic: during save and load to/from tape, a line-break was visible on border stripes at first screen's pixel column.

SPI logic (already present for sdcard access) mapped to on-board SPI devices such as the M25P16 flash, from which the Spartan 3E could read it's power-up configuration bits. A tiny Bootloader reads the SPI flash at fixed address $100000 (1MB offset) and, if a ZX-Spectrum rom is found, 16KB are copied to internal blockram and boot is performed. There is no longer need to boot from serial port. Note that the SPI flash should be programmed through iMpact as no write routine is provided yet. The SPI flash can be accessed by ZX-Spectrum's basic commands IN and OUT to proper SPI ports implemented in the FPGA (see I/O registers).

Preliminary test of a modified version of ZX-Badaloc BootRom. The main menu` displays and asks the user to initialize the sd-card. Unfortunately, no sd-card slots are connected to the fpga yet. Furthermore, no DDR access is available so the bootrom can do very little.

A working Tape interface has been designed and connected to Xilinx board connector J1. Schematic and photos are available in the Download Page. The interface schematic is the same designed for the original Clone. Two 16K games (Space Raiders and Space Panic) successfully loaded from tape and run on the Xilinx board. The machine works as a 16K Spectrum thanks to the 8K+8K video blockram, temporarily mapped on $4000 - $7FFF.

PS/2 Keyboard up and running: all ZX-Spectrum keys are working and remapped to a PS/2 keys. A few special keys are used as shortcut (for example, backspace).The ZX-Badaloc clock_select register, now accessible through keyboard and Sinclair Basic's OUT command, allows the following clock speeds: 3.5 - 7 - 14.125 - 21.25 - 28.33 - 42.5MHz.

Thanks to an hint from
Mike Johnson of the T80 team, a modified T80 wrapper from FpgaArcade's Pacman has been used in place of the original one, solving the issue on Z80 timings: the original wrapper always runs the processor in enhanced mode (1 T-state I/O and memory access), posing a compatibility problem.

Another 16K blockram mapped at 0 - $3FFF, acting as temporary system ROM (since the DDR chip is not usable yet). This 16K block can be write protected and will be swapped-in with a specific I/O command (see the Register's Page).
A tiny Bootloader written in Z80 code has been synthesized into the VHDL logic: at power on, the Border color is cycled and the program waits for a 16K stream from the RS-232 port: this is the same, 115K2 baud serial port built into the I/O CPLD of the original project now mapped to the onboard female DB9 connector. A new "Fpga" menu in the ZX-Com program let the user load a 16K binary ROM file from disk and send it to the Z80 living into the FPGA, which will save it to this 16K block. Then, the bootloader is swapped out and a Jump to the uploaded ROM is performed. This successfully displays the Sinclair Research Ltd. logo when a 16/48K Spectrum rom is uploaded.

This Video shows the described process: starting the board by uploading the project (border color cycles, waiting for rom upload) then the rom upload and Sinclair Logo on screen. By now there is no support to anything else. The PS/2 keyboard is in progress.

The XC9572 "I/O" cpld from ZX-Badaloc istantiated as a component. This "device" gives a 115K2 baud RS-232 port (mapped to the female DB9) capable of generating NMI on RX, plus two SPI ports for sd-card access. A third SPI chip select is spare and reserved for possible implementation of a spi-controlled ethernet interface. The serial port has been successfully tested.

50Hz Z80 Interrupt logic added (synchronized to the screen vertical refresh rate, as on the ZX-Spectrum).

A Z80 processor has been added to the project: it is the www.opencores.org T80. Since no rom memory is present and the bus floats to $FF, running the processor generates the typical blue/black/white vertical stripes caused by endless stack pushing of the return address from RST $38 instruction (which has opcode $FF). A little piece of Z80 code has then been added, synthesized into the VHDL, which increments a 24-bit variable on screen memory (visible). Problem: no matter what is specified in the wrapper, the processor always runs in enhanced mode (1 T-state for I/O and memory access). This will cause compatibility problems.

A ZX-Spectrum-like video memory has been implemented into two 8Kb memory blocks inside the FPGA (dual frame buffer for 128K Spectrum implementation). This eliminates the need of the expensive 32K dual port ram installed on original ZX-Badaloc. Since no external memory has been activated yet (the board is equipped with a 64MB DDR chip), the current project maps the entire 16K framebuffer at contiguous locations between $4000 and $7FFF, for preliminar Z80 operation.
The 85MHz main clock signal is generated by the Fpga DCM from the 50MHz oscillator. This eliminates the need of the programmable 85MHz osc.
VGA output works perfectly (no brightness supported yet) at 31.25KHz/50Hz thanks to a line scan frequency doubler built into the FPGA using a 512 bytes ram block. This eliminates the need of the external 128K static ram which in the original ZX-Badaloc is used to double the vertical frequency to 100Hz. As a side effect, LCD monitors may now lock to the signal (while 100Hz were too much and only CRT could be used). The standard 256 by 192 pixels with border are displayed.


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