ZX-Badaloc     Reloaded

Implementing the ZX-Badaloc Clone into an FPGA

Memory MAP


All the clone memory is provided by two devices: the 64MB DDR chip and the internal FPGA Blockram (16K are used as video memory). The DDR is divided into 64 1-megabyte chunks. The blockram is used for BootRom firmware (16K) and video memory (16K, divided into two 8K blocks for dual screen mode of the 128K spectrum). The first video memory block from blockram is mapped on $4000 - $5FFF (8K), which is also accessible as BANK_5 on a 128K spectrum. The other 8K block is on BANK_7. Selecting this bank will map the second 8K chunk of blockram on $C000-$DFFF area. Everything else comes from the DDR chip.

At the topmost addressing level, the DDR_MSB register selects one 1MB memory block out of 64. Changing the DDR_MSB register only affects 'FASTPAGE' addressing (16K paging into 0-$3FFF or $C000-$FFFF area) while normal access will only deal with first megabyte, combined with the blockram as seen above. In normal operation, DDR_MSB register is deactivated so the first megabyte is always accessed.

Within this megabyte of address space, DDR memory is divided into 64 blocks of 16K each. For compatibility reason, the lower 32 blocks are referred as 'RAM' and the upper 32 as 'ROM'.

Here is a list of modes available to map these 64 blocks into the 64K Z80 addressing space. Since 128K ZX-Spectrum has 8 RAM_BANKS (16K each) which can be paged-in, we refer to them as "RAM_BANK n. X" where X ranges from 0 to 7.


0 - $3FFF

This is normally the "ROM" region in standard ZX-Spectrum machines.

When the clone operates normally:

A "ROM" 16K bank out of 32 blocks (upper 512K area) can be mapped in this region, as follows:

A18:A16    Upper block select: these nonstandard address bits come from D5:D3 of the $24DF register
A15        As on 128K +2A/3A, this is the standard upper memory select bit (+2A/+3 machines have 4 x 16K roms)
A14        As on 128K machines, this comes from the $7FFD register (ROM 0/1 select)

The A15:A14 bits are from standard registers, allowing any ZX-Spectrum model implementation.

When a 'context switch' takes place (NMI or software driven):

A 16K block from FPGA internal blockram is immediately mapped in order to handle a NMI request. DDR is disabled. This blockram is loaded at startup with the BootRom Firmware from SPI Flash chip by the tiny bootloader (see below). Bootrom firmware includes a NMI handler and power-on main menu' for snapshot load and general clone setup tasks. The context mode is enabled by default at power-on.

When FASTPAGE is enabled by setting D6 of $54DF register:

The FASTPAGE is a way to access the entire 1MB (64MB using DDR_MSB register in conjunction with fastpage) into the 0-3FFF area by just selecting the desired bank in the fastpage register. Note that only DDR chip is accessed: blockram is not involved. This means that the DDR area normally shadowed-out by blockram in the video region can be accessed by this register. See the FASTPAGE and DDR_MSB registers for further details.

When ZX-Spectrum +2A / +3 special paging mode is enabled:

In this mode, "ROM" is not used. The entire 64K address space is populated by 128K ram banks, accordingly with +2A / +3 specification.

Immediately at Power-ON:

A tiny bootloader, embedded into the VHDL code programmed in the FPGA, is mapped into this region. It will show a border color cycle and every 8 colors will attempt to load a 16K ROM image from the SPI Flash into the 16K blockram. If this succeeds, the found rom will become the 'system firmware'. The tiny bootloader then swaps itself out forever by writing to the $44DF register and performa a JP 0.

The SPI boot can be disabled by turining on the SW0 on the board. In this case, the border will cycle forever. While cycling, the Win32 ZX-Com program allows booting a ROM or programming a Xilinx .bit file into the SPI Flash through RS-232.


$4000 - $7FFF

This is the first 16K RAM area. The first screen buffer, on RAM_BANK 5, is normally paged here.

In order to have two possible video banks as required by ZX-Spectrum 128 (the first in BANK 5 and the other in BANK 7) the available 16K blockram is divided into two 8K chunks. The screen takes 6912 bytes, so it will fit within the first 8K (who are provided by blockram, configured as dual port). The remainder comes from the DDR bank which normally (if no blockram were used) would be entirely mapped in (bank 5 or 7).

Other banks are accessible if +2A / +3 special mode is enabled (refer to original zx-spectrum documentation)


$8000 - $BFFF

This area is always mapped to RAM_BANK 2 (from DDR).

Other banks are accessible if +2A / +3 special mode is enabled (refer to original zx-spectrum documentation)


$C000 - $FFFF

This is the topmost memory area on Z80-based machines. The 128K spectrum is capable of mapping it's 128K of RAM in this area by a bank select register.

When the clone operates normally:

One 16K bank out of 8 RAM_BANKS, selected by $7FFD register as on the ZX-Spectrum 128K

Other banks are accessible if +2A / +3 special mode is enabled (refer to original zx-spectrum documentation)

When FASTPAGE is enabled by setting D6 of $54DF register AND the new "special mode" (D7 on $34DF register) is set:

When D7 on $34DF register is SET, FASTPAGE takes place on $C000 - $FFFF instead of the standard 0 - $3FFF area. This feature was not available on the original zx-badaloc clone and has been implemented in order to access the entire 64MB DDR memory without affecting the 0-3FFF address space, allowing (for example) the bootrom firmware (which works in blockram at 0-$3FFF) to run while accessing the DDR memory for tasks such as SPI programming/comparing, RS-232 memory transfer, etc.

This also enables a basic program to access 64MB banked on $C000 - $FFFF area, using FASTPAGE and DDR_MSB registers to select the desired bank. A simple CLEAR 49151 will prevent the Sinclair ROM from using that area for basic interpreter, then fastpaging can be safely enabled.

The fastpage works as usual, but the memory is mapped in the $C000 - $FFFF space.

The only exception regards the WR protection bit (D7 in the Fastpage register): when accessed here, the memory is ALWAYS write enabled.


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